Heretofore, a delay locked loop (DLL) circuit has been known as one means such as a frequency multiplier.
The DLL is a circuit which controls and adjusts, by a circuit technology, a time difference (a phase difference) between a reference clock signal (an input signal) provided from the outside and an inner clock signal, to generate a clock signal at a high speed and a high operation frequency.
The objects of using the DLL include reduction of a lock-up time, improvement of precision of a delay amount and the like from the viewpoints of a function, and the like, and to achieve these objects, a DLL of digital control has been proposed instead of a conventional DLL of analog control (e.g., see International Publication No. W003/036796).
Here, a circuit constitution example of the conventional DLL will be described with reference to FIGS. 19(i), (ii). FIG. 19(i) is a block diagram showing a conventional DLL circuit constitution, and FIG. 19(ii) is a graph showing a change of each signal with time in the conventional DLL.
As shown in FIG. 19(i), a conventional DLL 100 includes a delay circuit 110, a phase comparator 120, a counter 130 and a DA converter (DAC) 140.
The delay circuit 110 has a constitution in which a plurality of delay elements each having an equal delay amount are connected in series, and supplies a predetermined delay amount to an input signal (a reference signal, an input clock in FIG. 19) to generate the delayed signal as an output signal.
The phase comparator 120 inputs the output signal (an output waveform) of the delay circuit 110 together with the input signal (an input waveform). Then, a value of the output signal is detected in synchronization with the input signal. This detection result is output as a phase signal indicating an advance or a delay of a phase of the output signal with respect to the input signal (FIGS. 19(ii)(a), (b) and (c)).
The counter 130 has a function of a priority encoder, and produces a control signal constituted of a plurality of bits in accordance with the phase signal from the phase comparator 120 (FIG. 19 (ii) (c) , (d)).
The DA converter (a delay time acquiring section) 140 receives the control signal from the counter 130 and outputs a delay time signal indicating a delay time corresponding to the bit value of the control signal.
Then, the delay circuit 110 adds a predetermined delay amount to the output signal, based on a delay time signal input from the DA converter 140. Here, when a large number of bits indicate “H” in the delay time signal, the delay circuit 110 increases the delay time of the output signal with respect to the input signal. On the other hand, when a small number of bits indicate “H” in the delay time signal, the delay time of the output signal with respect to the input signal is decreased. According to such an operation, the output signal having a constant delay amount with respect to the input signal can be generated.
In the conventional DLL, however, in a case where the number of the bits of a counter is increased so as to broaden a lock range, there has been a problem that the number of the bits becomes enormous.
On the other hand, in a case where a change amount (resolution) of the delay time with respect to a change of one bit of a counter value is increased so that the counter does not have the enormous number of the bits, there has been a problem that jitter cannot sufficiently be reduced.
To solve the problem, a technology in which the conventional DLL is improved is suggested.
A constitution of the DLL according to this improved technology is shown in FIG. 20.
As shown in the drawing, a DLL 200-1 includes, for example, a delay circuit 210 in which a plurality of delay elements each having an equal delay amount are connected in series, a plurality of phase comparators 220a, 220b which receive an input signal and an output signal of the delay circuit 210 to output a phase signal, a plurality of counters 230a, 230b which receive the phase signal from the corresponding phase comparator 220 to output a control signal, a plurality of delay time acquiring sections (DA converters (DAC)) 240a, 240b which receive the control signal from the corresponding counter 230 to output a delay time signal indicating a delay time corresponding to a bit value of the input control signal, an adding section 250 which adds up the delay time indicated by each delay time signal output from each of these delay time acquiring sections 240, and a delay time control section (a bias circuit) 260 which converts a delay time sum added up by the adding section 250 into the delay time of each delay element of the delay circuit 210.
In the example of FIG. 20, two phase comparators 220, two counters 230 and two DA converters 240 are provided, respectively. One of the components constitutes a fine (fine resolution) system, and the other component constitutes a coarse (coarse resolution) system. Here, as shown in FIG. 21, a small deviation from one period of the input signal is processed by a fine section. On the other hand, in a case where digit carrying or lowering occurs in the fine section or there is a large deviation from one period, a coarse section processes this case.
In consequence, the delay amount of the delay circuit 210 is controlled so that the amount is just one period of the input signal. In addition, the lock range can be expanded without increasing the number of the bits of the counter 230.
Furthermore, a sum of the delay time with the coarse resolution and the delay time with the fine resolution is reflected in the compensation of the deviation of the delay amount, so that a lock-up time can rapidly be reduced as compared with a case where the resolution of the counter 230 is simply increased.
However, in case of processing a noise having a large amplitude, the counter 230 causes overflow (the count value exceeds an upper limit of a predetermined range) or underflow (the count value exceeds a lower limit of the predetermined range). To avoid this, it is supposed that the number of the bits of the counter 230 is increased, however this has a demerit that a circuit scale enlarges.
To solve the problem, as shown in FIG. 22, a DLL 200-2 includes a control circuit (a controller) 270 which controls operations of counters 230a, 230b of the respective systems. Then, in a case where a count value exceeds a predetermined range in the fine system counter (a first counter) 230a and the coarse system counter (a second counter) 230b outputs a phase signal HOLD, the count value is set to a half value with respect to the counter 230a, and the value is counted up (digit carrying) or down (digit lowering) with respect to the counter 230b. 
Thus, a delay component having a small resolution and a delay component having a large resolution are subjected to digit carrying/lowering processing, whereby the lock range can be broadened without enlarging the circuit scale of the counter, and the overflow and underflow in the counter 230 can be avoided.
As described above, the conventional DLLs 200-1, 200-2 each including the fine section and the coarse section are very effective as means for solving the above problems, for example, so that a lock range can be broadened without enlarging a circuit scale of a counter as compared with the conventional DLL 100 including only one phase comparator or the like.
However, in the DLL, a delay amount of the delay circuit 210 largely fluctuates owing to a fluctuation of a CMOS process, a voltage and a temperature. For example, even with an equal set value of a DA converter, a delay amount sometimes exceeds 1.5 periods, and does not reach a 0.5 period. In this case, it is supposed that cycle slip might occur in an output signal of the delay circuit.
As shown in FIGS. 23, 24, the cycle slip is a phenomenon in which an output signal of the delay circuit has a delay amount larger or smaller than a predetermined range (e.g., a range of a 1.5 period delay to a 0.5 period delay) including a true delay amount (e.g., a delay amount of a 1 period delay) of the output signal of the delay circuit, and hence compensation is performed in a direction reverse to a correct compensating direction, thus it becomes impossible to compensate the delay amount.
It is to be noted that FIG. 23 shows a state in which the cycle slip occurs in a case where the delay amount of the delay circuit is larger than 1.5 periods, and FIG. 24 shows a state in which the cycle slip occurs in a case where the delay amount of the delay circuit is smaller than 0.5 period.
To avoid such cycle slip, heretofore the delay amount of the delay circuit is measured for each DLL circuit, and an appropriate counter initially set value is determined so that this delay amount is a value around the one period delay of an input signal.
However, in a conventional measurement method of the delay amount, the set value of the counter is switched one by one, and loaded, and the delay amount is measured for each switching, so that calibration of the delay circuit requires a long time.